The present invention relates in general to data processing systems, and in particular, to an inter-IC (I2C) bus in a data processing system.
The I2C bus is a 2-wire bidirectional serial bus for communication between bus devices in a data processing system. Bus devices may include microprocessors, microcontrollers, memory devices, peripheral devices, data converters, and application oriented circuits. Two wires of the I2C bus constitute a serial data line (SDA) for communicating data between bus devices, and a serial clock line (SCL) carrying clock signals that control bus access and data transfer.
Each device on the I2C bus is identified by a unique address. The least significant bit (LSB) of an address byte constitutes a read/write (R/W) bit that signals whether the current bus transaction is a read operation or a write operation. Of the remaining seven bits, four denote the functional group to which the bus device belongs, leaving three bits which may be freely assigned to form the unique address of the particular bus device. Thus, within a particular device group, or category, no more than eight devices from within the group may reside on a given I2C bus.
The limitation of eight devices from a given group on a single I2C bus significantly constrains a data processing system using an I2C bus. Thus, there is a need in the art for mechanisms and methods for expanding an I2C bus while operating within the I2C bus protocols.
The aforementioned needs are addressed by the present invention. Accordingly, there is provided in a first form, an apparatus for inter-IC (I2C) bus expansion. The apparatus includes an expansion processor operable for communicating on an I2C bus. The expansion processor is coupled to a plurality of I2C sub-buses, wherein each sub-bus of the plurality is operable for transferring data between the expansion processor and a plurality of I2C compatible devices, according to an I2C protocol, in response to signals on the I2C bus.
There is also provided, in a second form, a data processing system. The data processing system includes a central processing unit (CPU) operable for communicating on an inter-IC (I2C) bus, the CPU being operable as an I2C bus master. An expansion processor is coupled to the I2C bus, the expansion processor is also coupled to a plurality of I2C sub-buses, wherein each sub-bus of the plurality is operable for transferring data between the expansion processor and a plurality of I2C compatible devices, according to an I2C protocol, in response to signals on the I2C bus.
Additionally, there is provided, in a third form, a method for inter-IC (I2C) bus expansion. The method includes snooping a primary I2C for a preselected bus address. On receiving the preselected address, a read operation or a write operation on a sub-bus is selected in response to a data value in a portion of the address.
There is also provided, in a fourth form, a computer program product adaptable for storage on program storage media. The program product includes programming for snooping a primary I2C bus for a preselected bus address. The program product also includes programming for, on receiving the bus address, selecting a read operation or a write operation in response to a data value in a portion of the address.
The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention.